1. Field of the Invention
The present invention relates to a semiconductor device that is equipped with a high breakdown voltage transistor and a low voltage transistor, the side wall widths of which are different from each other and a method of manufacturing the same. More particularly, the invention concerns a semiconductor device wherein a high voltage drive circuit and a low voltage drive circuit are co-loaded on the same chip and a method of manufacturing the same. Further, the invention concerns a semiconductor device wherein a non-volatile memory cell array is integrated and a method of manufacturing the same.
2. Description of the Related Art
There has in recent years been an increasing demand for a semiconductor integrated circuit wherein, together with a non-volatile memory cell array, a logic circuit that is driven with a high speed is co-loaded on the same chip to thereby enhance the added value.
In this type of semiconductor device, as the peripheral circuits for a memory cell array, there is used a high breakdown voltage transistor that composes a drive circuit, etc. that handles a high voltage (program/erasure, etc.) that is needed for driving the memory cell, as well as a low voltage transistor circuit that composes a logic circuit, etc. that operates with a low voltage and with a high speed.
A high breakdown voltage transistor, as described above, is used to generate and transfer ten and odd volts of voltage as at the time of program/erasure operation with respect to the memory cell. In this connection, regarding a non-volatile memory, ensuring the reliability with which that memory becomes error-free with respect to the program/erasure that is performed several tens of thousands of times or more is demanded the most. For this reason, regarding the junction breakdown voltage of the high breakdown voltage transistor that handles a high level of voltage, it is necessary to sufficiently ensure such junction breakdown voltage.
For solving the above-described problems, in the official gazette of Japanese Unexamined Patent Publication No. 2001-93984, there is disclosed a method of individually separately fabricating the side wall width, namely structuring in such a way that the side wall width of the high breakdown voltage transistor is made wider than the side wall width of the low voltage transistor. The conventional manufacturing process that is disclosed in the official gazette of Japanese Unexamined Patent Publication No. 2001-93984 will briefly be explained using FIGS. 11 to 14. Incidentally, in these figures, the figures (a) illustrate a sectional view of process step for the high breakdown voltage transistor while the figures (b) illustrate a sectional view of process step for the low voltage transistor.
First, as shown in FIGS. 11(a) and 11(b), with respect to a semiconductor substrate 101 that has an element isolation region 102, an N well 103 and P well 104 of the high breakdown voltage transistor region (a), and an N well layer 118 and P well layer 119 of the lower voltage transistor region (b), there are formed the element isolation regions 102, gate insulation films 109 and gate electrodes 110b for the low voltage transistor, as well as gate insulation films 108 and gate electrodes 110a for the high breakdown voltage transistor.
Next, as shown in FIGS. 12(a) and 12(b), selective LDD injection (impurity injection) is performed, using the respective gate electrodes as masks, with respect to the low voltage transistor and high breakdown voltage transistor to thereby form LDD regions 111 and 120. Incidentally, when forming this LDD region, it is formed more deeply on the high breakdown voltage transistor side than on the low voltage one side.
Next to this, as shown in FIGS. 13(a) and 13(b), a first insulative film 112 for use as the side wall that consists of a silicon oxide film, silicon nitride film, or the like is formed. Then, the insulative film 112 in the region for forming therein the low voltage transistor is removed, to thereby leave the insulative film in only the high breakdown voltage transistor region. Here, for that partial removal of the first insulative film 112 in the low voltage transistor region, there is employed a method wherein a photo-resist 115 having an opening in only the low voltage transistor region is formed; and, using it as the mask, wet etching is performed up to midway in the insulative film; and thereafter dry etching is performed to thereby perform that removal. Or, alternatively, there is employed a method wherein, using a silicon nitride film or silicon nitride oxide film as the insulative film, it is arranged that, even when a technique of anisotropic etching is used, the backing element isolation insulative film 102 be prevented from being excessively etched.
Next to this, a second insulative film 113 is deposited on the entire surface of the substrate, then the entire resulting surface of it is etched back. As a result of this, side walls the widths of that are different from each other are formed, respectively, with respect to the low voltage transistor region and high breakdown voltage transistor region.
Thereafter, as shown in FIGS. 14(a) and 14(b), using the gate electrode and side walls as the mask, there is performed injection of the high-concentration impurity for forming the source and drain regions. Then, although not illustrated, the resulting surface of the substrate is salicided to thereby perform covering an insulative film over the entire resulting surface using a CVD technique or the like. Then, contact holes are formed there and an electrically conductive film is embedded into there, and prescribed electrodes are connected to there, thereby a semiconductor device that is equipped with the high breakdown voltage transistor and low voltage transistor is obtained.
In a case where using this conventional technique, in the high breakdown voltage transistor, the low-concentration diffusion layer (LDD) is deeply diffused and simultaneously the distance from the high-concentration diffusion layer (source/drain region) to the forward end of the low-concentration diffusion layer is taken to be long. As a result of this, the depletion layer become easy to get spread, with the result that a sufficiently high level of junction breakdown voltage is ensured. On the other hand, in the low voltage transistor, it is possible to form a high-performance logic transistor in that, by the shallow LDD layer, there is suppressed the loss of the driving electric current as well as the deterioration in the short channel characteristic.
However, in the above-described conventional method, in a case where the non-volatile semiconductor memory device and low voltage logic circuit have been co-loaded on the same one chip, the following inconvenience arises. Namely, when eliminating the first side wall film in the low voltage transistor region, since there is not the stopper film, or the like, that protects the element isolation insulative film, it is in actuality difficult, regarding stopping etching at the position of element isolation insulative film, to perform control for that stopping. This raised the problem that, during the manufacturing process steps, the element isolation insulative film was excessively etched and in consequence it caused deterioration of the element-isolating performance.
In addition, when in the low voltage transistor as in the case of the high breakdown voltage transistor LDD injection for forming the low-concentration region is performed after forming the gate electrode, in the heat treating process step that is performed, for example, at the time of thereafter forming the side walls the impurity is diffused right under the gate or the concentration becomes thin. Resultantly, the short channel effect becomes great or the performance of the transistor deteriorates, such as, the driving electric current becomes insufficient. These obstructed micronizing the transistor.
On the other hand, injecting the LDD in the low voltage transistor with the first side wall film being left thereon as is causes the following inconvenience. Even after the execution of the thereafter-succeeding heat treatment, since the low-concentration diffusion region has difficulty going around into up to right beneath the channel, this causes the increase in the effective channel length. This is followed by the rise in the threshold voltage as well as by the deterioration in the electric current driving ability of the transistor. This disables obtaining a desired transistor.